1. Field of the Invention
The present invention relates to a method of manufacturing a high-performance ultra-miniaturized bipolar transistor and, more particularly, to a method of forming a base region and an emitter region by self alignment.
2. Description of the Prior Art
A high performance bipolar transistor is required in various fields such as computers, optical communication, and various analog circuits. Especially, an ultra-miniaturized bipolar transistor which has a high cut-off frequency and can be integrated in an LSI is required.
In order to manufacture the above ultra-miniaturized bipolar transistor, several techniques for forming a base region and an emitter region by self alignment have been recently proposed. Cut-off frequencies of bipolar transistors manufactured by these techniques almost reach 30 GHz.
(1) IEEE Trans. on Electron Devices, Vol. ED-33, No. 4, Apr. 1986, p.526, PA1 (a) forming an insulating film on a semiconductor wafer having a collector region of a first conductivity type; PA1 (b) depositing a first mask material film on the insulating film, and patterning the first mask material film, thereby forming a first mask material film pattern covering an internal base region prospective portion, the first mask material film pattern having a step at its end portion with respect to a surrounding wafer surface; PA1 (c) depositing a conductive material on the surface to cover the first mask material film pattern, thereby forming a first conductive film to be used as a part of a base electrode, the surface of the first conductive film having a recess at a position spaced apart from a side end of the first mask material film pattern in a transverse direction by a distance corresponding to the film thickness of the first conductive film; PA1 (d) burying a second mask material film pattern in the recess of the first conductive film surface; PA1 (e) selectively etching the first conductive film using the second mask material film pattern as an etching mask to expose the first mask material film pattern; PA1 (f) continuously, selectively etching the first conductive film by etching using the exposed first mask material film pattern and the second mask material film pattern as etching masks, thereby forming a first opening for forming an external base region between the two mask material film patterns; PA1 (g) removing the second mask material film pattern; PA1 (h) burying a second conductive film serving as a part of a base electrode in the first opening, while doping an impurity of a second conductivity type into the wafer through the first opening to form the external base region of the second conductivity type; PA1 (i) removing the first mask material film pattern to form a second opening for forming an internal base region; PA1 (j) forming a thermal oxide film on the surface of the second conductive film; PA1 (k) doping an impurity of the second conductivity type into the wafer through the second opening to form the internal base region of the second conductivity type; and PA1 (l) doping an impurity of the first conductivity type into the wafer through the second opening.
(2) Japanese Patent Disclosure (Kokai) No. 58-7862,
(3) ISSCC87, 1987, p.58.
Typical conventional techniques and their problems will be described below.
FIGS. 1A to 1D show manufacturing steps in one conventional technique. As shown in FIG. 1A, a wafer has n.sup.+ -type buried region 22 formed on p-type Si substrate 21 and n-type epitaxial layer 23 formed thereon. P-type channel stopper region 24 is formed in element isolation region of the wafer, and field oxide film 25 is formed by selective oxidation. Thin thermal oxide film 26 is formed on the surface of an element region of the wafer, nitride film (Si.sub.3 N.sub.4 film) 27 serving as an anti-oxidation mask is deposited, and then first polycrystalline silicon film 28 is deposited. Subsequently, film 28 is selectively, thermally oxidized to change an unnecessary portion on the element isolation region into oxide film 29. Then, boron is doped in film 28 by ion implantation. Thereafter, film 28 is selectively etched by photoetching to form an opening in an emitter formation region as shown in FIG. 1A.
Then, as shown in FIG. 1B, the resultant structure is heat-treated in an oxygen atmosphere to form oxide film 30 on the surface of film 28, and then film 27 at the opening portion is etched by a heated aqueous phosphoric acid solution, using film 30 as a mask. Thereafter, exposed film 26 is removed by an aqueous NH.sub.4 F solution to expose the wafer surface. At this time, by intentionally over-etching film 27, overhang portion 31 is formed along an edge of film 28 as shown in FIG. 1B.
Then, second polycrystalline silicon film 32 is deposited on the entire surface, and embedded in overhang portion 31. Subsequently, the second polycrystalline film 32 is etched, thereby exposing the oxide film 30 and the surface of the wafer in the opening, as shown in FIG. 1C.
Then, the exposed wafer surface and a side surface of film 32 as shown in FIG. 1C, are thermally oxidized to form thermal oxide film 33, as shown in FIG. 1D. During thermal oxidation, the boron doped in film 28 is diffused into the wafer through film 32, thereby forming p-type external base region 34. Subsequently, boron is ion-implanted through the opening portion to form p-type internal base region 35. Thereafter, CVD insulating film 36 and third polycrystalline silicon film 37 are deposited and then etched back by reactive ion etching so that films 36 and 37 remain on side walls of the opening portion. Then, film 33 on the wafer surface at the opening portion is etched using residual film 37 as a mask to expose the wafer surface. Thereafter, fourth polycrystalline silicon film 38 doped with arsenic having a high concentration is deposited and annealed. At this time, the arsenic in film 38 is diffused into the wafer to form n-type emitter region 39, thereby obtaining a bipolar transistor shown in FIG. 1D. Note that first and second polycrystalline silicon films 28 and 32 are used as a base electrode, and fourth polycrystalline silicon film 38 is used as an emitter electrode.
According to the above method shown in FIGS. 1A to lD, the base and emitter regions are formed by self alignment. In addition, since a structure is miniaturized, i.e., the width of an emitter diffusion window is as small as 0.35 .mu.m, a bipolar transistor having excellent high-speed operation characteristics can be obtained. However, according to this method, it is difficult to control the size of overhang portion 31 in FIG. 1B. That is, in a step of etching nitride film 27 by an aqueous phosphoric acid solution to form overhang portion 31, it is difficult to control conditions such as a temperature, a concentration of the phosphoric acid, and a stirring state . For this reason, the size of overhang portion 31 varies in different wafers and in each individual wafer, resulting in variations in element characteristics.
In the step of FIG. 1C, when second polycrystalline film 32 is etched to be buried below overhang portion 31, the wafer surface formed also of silicon is simultaneously etched. Therefore, the wafer surface of the emitter region is damaged. In addition, the width of the polycrystalline silicon film (which largely affects the width of the external base region) to be buried below the overhand portion varies, resulting in variations in characteristics such as a breakdown voltage and a cut-off frequency.
FIGS. 2A to 2D show manufacturing steps of another conventional method. In this method, as shown in FIG. 2A, n.sup.+ -type buried region 42 is formed on p-type Si substrate 41 to grow n-type epitaxial layer 43. P-type channel stopper region 44 is formed in an element isolation region, and thick field oxide film 45 is formed. The above steps are the same as in the above conventional method. Thereafter, nitride film 46 serving as an anti-oxidation mask and CVD oxide film 47 are sequentially deposited on the entire surface and patterned so that films 46 and 47 remain in an emitter region of an element and the element isolation region.
Then, as shown in FIG. 2B, first polycrystalline silicon film 48 is deposited on the entire surface, and boron is ion-implanted in film 48. Subsequently, thick photoresist film 49 is formed on the surface of film 48, and the entire surface is flattened. Thereafter, the thick photoresist film is etched back. As a result, as shown in FIG. 2B, film 48 on film 47 is exposed, and photoresist 49 is buried in the recess of film 48.
Then, film 48 is etched using photoresist 49 as a mask to expose the surface of film 47. Thereafter, CVD insulating film 47.sub.1 at a portion serving as an emitter region is removed, and thermal oxidation is performed using film 46 as a mask, thereby forming oxide film 50 on the surface of film 48. At the same time, the boron in film 48 is thermally diffused into the wafer to form p-type layer 51 serving as an external base region as shown in FIG. 2C.
Thereafter, film 46 is removed by a heated aqueous phosphoric acid solution to form an emitter opening portion. Then, as shown in FIG. 2D, second polycrystalline silicon film pattern 53 for burying the emitter opening portion is formed. Boron is ion-implanted in film 53 at a high concentration and annealed, thereby diffusing the boron into the wafer to form internal base layer 52. Then, arsenic is ion-implanted in film 53 at a high concentration and annealed, thereby diffusing the arsenic into the wafer to form n-type emitter layer 54. As a result, an npn transistor is completed.
In the conventional method shown in FIGS. 2A to 2D, unlike in the conventional method shown in FIGS. 1A to 1D, no overhang portion is formed and therefore a polycrystalline silicon film is not buried below the overhang portion, i.e., manufacturing steps difficult to be controlled are not present. In addition, the emitter and internal base layers can be formed by self alignment.
However, according to the conventional method shown in FIGS. 2A to 2D, a relationship between external base region 51 and emitter region 54 cannot be completely defined by self alignment. This is because a portion from CVD insulating film 471 which defines the emitter region to insulating film 45 is entirely the external base region as shown in FIG. 2C. Therefore, if mask alignment for forming CVD insulating films 47.sub.1 to 47.sub.3 is offset in FIG. 1A, widths of external base region 51 differ from each other at right and left sides of emitter region 54, resulting in variations in the element characteristics. In addition, in order to form CVD insulating film 47.sub.1 for defining the emitter region, a mask alignment margin must be assured in a photolithography step. For this reason, the external base region is enlarged to increase the size of the element as a whole. As a result, an unnecessary stray capacitance or parasitic resistance is increased.
As described above, according to the conventional methods of manufacturing a high-performance bipolar transistor, it is difficult to control formation of an overhang portion, or self alignment is incomplete. Therefore, a bipolar transistor which stably performs a high-speed operation cannot be obtained.